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SUMMIT
MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
See Last Page
Programmable -48V Hot-Swap Controller with Forced Shut Down
FEATURES & APPLICATIONS
l Soft Start Power Supply l Live Insertion into a -48V backplane l Programmable Control of a DC/DC Converter w I2C Power On/Off Control l Highly Programmable Circuit Breaker w Active In-rush Current Limiting w Over-current Filter Circuit Breaker Immunity to Voltage Steps and Current Spikes l Programmable Forced Shutdown Timer l Internal Shunt Regulator Allows a Wide Supply Range l 14-pin SOIC and 16-pin SSOP packages APPLICATIONS l -48V Power Distribution w w w w Telecom Line Cards Central Office Switching High Availability Servers Hot Board Insertion
INTRODUCTION
The SMH4802 is designed to control in-rush current during hot swapping of plug-in cards operating in a distributed power environment. The device drives an external power MOSFET switch that connects the supply to the load and protects against over-current conditions that might disrupt the host supply. It also provides undervoltage and over-voltage monitoring of the host power supply. When the source and drain voltages of the external MOSFETs are within specification it will provide a Power Good logic output that can be used to enable a DC/DC converter. Additional features of the device include: temperature sense or master enable input, a 5V reference output for expanding monitor functions, and duty-cycle or latched over-current protection modes. An internal Shunt regulator allows a wide supply range. The SMH4802 -48V Hot-Swap Controller also features a simple software I2C Power On/Off Interface for remote power control applications. Programming of configuration, control and calibration values by the user can be simplified with the SMX3200 interface adapter and a windows based GUI supplied by Summit.
SIMPLIFIED APPLICATION DRAWING
-48V Ret
RD
4
5
14
SDA I2C Header
SCL
VDD
8
UV PG#
12
V+
Out+
On/ DC/DC Off V- Out-
9
OV
SMH4802
FS#
10
3
EN/TS VSS
7
CBSENSE VGATE
6 2
DRAIN SENSE 5VREF
1 11
-48V A
RS
VSS
2062 SAD
-48V B
Figure 1. The drawing illustrates the SMH4802 in a typical line-card application. It should be noted this is just an example, and the specific component values are purposely not shown. Pin numbers reflect SOIC package.
(c)SUMMIT MICROELECTRONICS, Inc., 2003 * 1717 Fox Drive * San Jose, CA 95131 * Phone 408-436-9890 * FAX 408-436-9897 * www.summitmicro.com Characteristics subject to change without notice 2062 2.3 6/19/03
SMH4802
Preliminary Information
GENERAL DESCRIPTION
The SMH4802 is an integrated power controller for hot swappable add-in cards. The device operates from a wide supply range and generates the signals necessary to drive an isolated output DC/DC converter. As a typical add-in board is inserted into the powered backplane, physical connections must first be made with the chassis to discharge any electrostatic voltage potentials. The board then contacts the long pins on the backplane that provide power and ground. As soon as power is applied, the device starts up, but does not immediately apply power to the output load. Under-voltage and over-voltage circuits inside the controller verify the input voltage is within the user-specified range. Once these requirements are met, the hot-swap controller enables VGATE to turn on the external power MOSFET. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the DRAIN SENSE input. When DRAIN SENSE drops below 2.5V, and VGATE is greater than VDD - VGT, the PG# output can begin turning on the DC/DC converter. Steady state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controller by shutting down the power MOSFET: an under-voltage or over-voltage condition on the host power supply; an overcurrent event detected on the CBSENSE input; a failure of the power MOSFET sensed via the DRAIN SENSE pin; the master enable (EN/TS) falling below 2.5V; or the FS# input being driven low by events on the secondary side of the DC/DC controller. If one of these events occurs the SMH4802 can be configured so VGATE shuts off and either latches into an off state or recycles power after a cooling down period, tCYC.
FUNCTIONAL BLOCK DIAGRAM
VDD 14
12VREF PROGRAMMABLE SHUTDOWN TIMER +
10 FS#
DRAIN 1 SENSE
-
11 5.0VREF
200k
EN/TS 3
+ Prog. Ref. -
+ - PROGRAMMABLE DELAY
12 PG#
UV 8
OV 9
5V 12V 2.5V
VSS 7
50k
50k
SCL 5 SDA 4
I2C INTERFACE LOGIC
PROGRAMMED DELAY
50mV
+ - DUTY CYCLE TIMER
CBSENSE 6 PROGRAMMED Quick-Trip
+ -
Figure 2. Functional Block diagram. Pin numbers reflect SOIC package.
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2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc.
+ - OV/UV FILTER PROGRAMMABLE DELAY VGATE SENSE
2 VGATE
2062 BD
SMH4802
Preliminary Information
PIN CONFIGURATION
14-Pin SOIC DRAIN SENSE VGATE EN/TS SDA SCL CBSENSE VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD nc PG# 5VREF FS# OV UV
2062 14 PCon 2062 16 PCon
16-Pin SSOP DRAIN SENSE VGATE EN/TS nc SDA SCL CBSENSE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD nc PG# nc 5VREF FS# OV UV
PIN DESCRIPTIONS
Pin No. Type Pin Name DRAIN SENSE Pin Description The DRAIN SENSE input monitors the voltage at the drain of the MOSFET (the measure is with respect to VSS). An internal 10A source pulls the DRAIN SENSE signal towards the 5VREF level. DRAIN SENSE must be held below 2.5V to enable the PG# output. The VGA E output is a high side drive output, nearly equal to VDD, used to turn T on an external power MOSFET This signal supplies a constant current output . (100A typical) which allows easy adjustment of the MOSFET turn-on slew rate. The ENable/T mperature Sense input is the master enable input. VGA E will be e T disabled if EN/TS is less than 2.5V This pin has an internal 200k pullup to 5V . . SDA is the bidirectional serial data pin. It is configured as an open drain output. There is an internal 50k resistor connected to 5VREF . The SCL input is used to clock data into and out of the configuration registers. In the write mode data must remain stable on SDA while SCL is HIGH. In the read mode data is clocked out on the falling edge of SCL. There is an internal 50k resistor connected to 5VREF .
1
I
2
O
VGA E T
3 4
I I/O
EN/TS SDA
5
I
SCL
6
I
The Circuit Breaker SENSE input is used to detect over-current conditions across an external, low value sense resistor (RS) tied in series with the power MOSFET . CBSENSE A voltage drop of greater than 50mV across the resistor for longer than tCBD will trip the circuit breaker. T disable CBSENSE connect the pin directly to VSS. A o programmable Quick-T ip sense point is also available. r VSS VSS is connected to the, negative side of the supply. All inputs and the 5VREF output are referenced to VSS. The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGA E will be disabled if UV is less than 2.5V T . A programmable internal hysteresis is available on the UV input, adjustable in increments of 62.5mV A filter delay is also available on the UV input. .
7
PWR
8
I
UV
Note: Pin numbers reflect the 14 Pin SOIC package.
2062 Pin Table A
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
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SMH4802
Preliminary Information
PIN DESCRIPTIONS (Continued)
Pin No. 9 Type I Pin Name OV Pin Description The OV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGA E will be disabled if OV is greater than T 2.5V A filter delay is also available on the OV input. . The Forced Shutdown pin is an active low input that causes VGA E and the PG# T output to be shut down at any time after an internal hold-off timer has expired. The hold-off timer allows supervisory circuits on the secondary side (which are not powered up initially) to control shut down of the SMH4802 via an optoisolator. This input has no pullup resistor. This is a 5V output reference voltage that may be used to expand the logic input functions on the SMH4802. The reference output is with respect to VSS. PG# is an open-drain, active-low output with no internal pullup resistor. It can be used to switch a Ioad or enable a DC/DC converter. PG# is enabled after 3 events: VGA E reaches VDD - VGT , the Drain Sense voltage is less than 2.5V T , and the programmed delay time has expired. V ltage on this pin cannot exceed o 12V as referenced to VSS. No connection VDD is the positive supply connection. An internal shunt regulator connected between VDD and VSS develops approximately 12V that supplies the SMH4802. A resistor Must be placed in series with the VDD pin to limit the regulator current (RD in the application illustrations).
2062 Pin Table B
10
I
FS#
11
O
5VREF
12
O
PG#
13
nc
nc
14
PWR
VDD
Note: Pin numbers reflect the 14 Pin SOIC package.
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SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ..................... -55C to 125C Storage Temperature .......................... -65C to 150C Lead Solder Temperature (10 secs) .................. 300C Terminal Voltage with Respect to VSS: VDD ............................................. -0.5V to VDD OV, UV, DRAIN SENSE, SCL, SDA, FS#, CBSENSE ........................ -0.5V to VDD +0.5V EN/TS ....................................................... 10V PG# .................................. -0.5V to VDD +0.5V VGATE ........................................... VDD +0.5V RECOMMENDED OPERATING CONDITIONS Temperature Range ............ (Industrial) -40C to 85C .......................................... (Commercial) -5C to 70C TJ(Max) ................................................................ 150C RJ-A ..................................... * Q 88C/W; R 115C/W RJ-C ....................................... * Q 37C/W; R 40C/W
Note -- The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. * Q 14 pin SOIC; R 16 pin SSOP.
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to VSS, except VGT)
Symbol VDD 5VREF ILOAD5 IDD VUV VUVHYST VOV VOVHYST VGATE IGATE VSENSE ISENSE VCB Parameter Supply voltage 5V reference output 5V reference output current Power supply current Under-Voltage threshold Under-Voltage hysteresis Over-Voltage threshold Over-Voltage hysteresis VGATE output voltage VGATE current output DRAIN SENSE threshold DRAIN SENSE current output Circuit breaker threshold Programmable Quick Trip circuit breaker threshold Off VEN/TS VEN/TSHYST VOL IIL VGT EN/TS threshold EN/TS hysteresis Output low voltage PG# Input current EN/TS Gate threshold (VGT = VDD - VGATE) IDD = 3mA IDD = 3mA IOL = 3mA VIL = VSS 0.7 0 100 1.8 3.0 2.475 2.500 10 0.4 2.525 IDD = 3mA VSENSE = VSS IDD = 3mA 2.475 -9 40 100 2.500 -10 50 200 VQCB 100 60 2.525 -11 60 IDD = 3mA IDD = 3mA IDD = 3mA IDD = 3mA 2.475 Conditions IDD = 3mA IDD = 3mA IDD = 3mA Min. 11 4.75 -1 2 2.475 2.500 63 2.500 10 VDD 2.525 Typ. 12 5.00 Max. 13 5.25 1 10 2.525 Units V V mA mA V mV V mV V A V A mV mV mV mV -- V mV V A V
2062 Elect Table
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
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SMH4802
Preliminary Information
AC OPERATING CHARACTERISTICS
Symbol Description Min. Typ. 5 50* tCBD Programmable 50mV Circuit Breaker Delay (filter) 150 400 5* 20 tPGD Programmable Power Good Delay 80 160 tQTSD tCYC Quick T ip Shut Down r Circuit breaker cycle time 5 Off* 5 tPUVF Programmable Under-/Over-V ltage Filter o 80 160 0.5 tSD Startup Delay Q 5 80 * 160
* = Default value
Q After UV and OV become valid there is a delay -- tSD -- that precedes the turn on of VGATE. See Figure 6. R Fast Shut Down delay from Fault to the beginning of VGATE off.
Max.
Units
s
ms
200 2.5
ns s s -- ms ms ms ms ms ms ms
2062 AC Table
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SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time Noise suppression 250 0 100 5 SCL low to valid SDA (cycle n) SCL low (cycle n + 1) to SDA change Before new transmission Conditions Min. 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2 1000 300 3.5 Max. 100 Units kHz s s s s s s s s ns ns ns ns ns ms
2062 Intf. Table
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
Figure 3 shows a timing diagram for the Bus Interface Memory timing. One bit of data is transferred during each clock pulse. Note that data must remain stable when the clock is high.
tR
tF
tHIGH
tLOW
SCL
tSU:SDA tHD:DAT tSU:DAT tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2050 Fig09 2.0
Figure 3. Bus Interface Memory Timing
SUMMIT MICROELECTRONICS, Inc. 2062 2.3 6/19/03
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SMH4802
Preliminary Information
APPLICATIONS INFORMATION
Powering VDD The 12V shunt regulator between the VDD and VSS pins allows the SMH4802 to operate over a wide range of supply voltages. It is necessary to use a series dropping resistor (RD) between the host power supply and the VDD pin in order to bias the shunt regulator and limit current into the device. System Enable The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistor divider network to sense when the host supply voltage exceeds the user defined limits. If the input to the UV pin rises above 2.5V, and the input to the OV pin falls below 2.5V, the power-up sequence may be initiated. If UV falls below 2.5V, or OV rises above 2.5V, the PG# and VGATE outputs will be shut down immediately. Under-/Over-Voltage Filtering The SMH4802 may also be configured so that an out of tolerance condition on UV/OV will not shut off the output immediately. A filter delay can be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. An out of tolerance condition on UV/ OV for longer than the filter delay time (tUOFLTR) will latch the VGATE and PG outputs in the off state if the UV/OV filter option is enabled. The Under-/Over-Voltage Filtering feature is disabled in the default configuration of the device. Under-Voltage Hysteresis The Under-Voltage comparator input may be configured with a programmable level of hysteresis. The compare level may be set in steps (up to 15) of 62.5mV below 2.5V. The default under-voltage hysteresis level is set to 62.5mV. Soft Start Slew Rate Control Once all of the preconditions for powering up the DC/DC converters have been met, the SMH4802 provides a means to soft start the external power FET limiting the in-rush current. Current limiting is generally needed due to the bulk capacitance across the power rails of the DC/DC converters. The VGATE output of the SMH4802 is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components.
8
Load Control -- Turning on a DC/DC Converter Once power has been ramped to the DC/DC converter, two conditions must be met before the PG# output can be asserted: the DRAIN SENSE voltage must be below 2.5V, and the VGATE voltage must be greater than VDD - VGT. The DRAIN SENSE input ensures the power MOSFET is not absorbing too much steady state power from operating at a high VDS. (This sensor remains active at all times, except during the current regulation period). The VGATE sensor ensures the power MOSFET is operating well into its saturation region before allowing the loads to be switched on. Once VGATE reaches VDD - VGT this sensor is latched. After the external MOSFET is properly switched on, the PG# output will be asserted after a delay of tPGD. The delay time is programmable from 5ms to 160ms. NOTE: The PG# output has a 12V withstand capability, so high voltages must not be connected to this pin. A bipolar transistor or an opto-isolator can be used to boost the withstand voltage to that of the host supply. Force Shutdown -- Secondary Feedback The Force Shutdown signal (FS#) is an active low input that provides a method of receiving feedback from the secondary side of the DC/DC controllers. A built-in holdoff timer allows the SMH4802 to ignore the state of the FS# input until the time period expires. The FS# input must be driven high by the end of this time period. If not, a low level on this input will shut off the VGATE and PG# outputs. The purpose of the hold-off timer is to allow enough time for devices on the secondary side of the DC/DC controller to power-up and stabilize. This unique feature of the SMH4802 allows supervisory circuits, such as an SMS44, to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. Circuit Breaker Operation The SMH4802 provides a number of circuit breaker functions to protect against over current conditions. A sustained over-current event could damage the host supply and/or the load circuitry. The board's load current passes through a series resistor (RS) connected between the MOSFET source (which is tied to CBSENSE) and VSS. The breaker trips (Figure 4) whenever the voltage drop across RS is greater than 50mV for more than tCBD (a programmable filter delay ranging from 10s to 500s).
2062 2.3 6/19/03
SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
APPLICATIONS INFORMATION (Continued)
2.5V UV
CBSENSE
tCBD 50mV
tPUVF
tCYC
VGATE
VGATE
2062 Fig05
2062 Fig04
Figure 4. Under-/Over-Voltage Filter Timing
Figure 5. Circuit Breaker Cycle Mode
Power-on Timing Figure 6 illustrates some power on sequences, including the UV and OV differentials to their reference, and Power Good cascading. Refer to the AC operating characteristics table for more information on the tCBD timing.
VDD
11 VDD 13 UV
tSD 2.5VREF OV
VDD - VGT VGATE VDD
5V DRAIN SENSE
2.5VREF
50mVREF CBSENSE PG#
tPGD
2062 Fig06
Note: In current regulation mode the DRAIN SENSE signal will not affect the PG# output.
Figure 6. Power On Timing Sequence
SUMMIT MICROELECTRONICS, Inc. 2062 2.3 6/19/03
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SMH4802
Preliminary Information
APPLICATIONS INFORMATION (Continued)
Quick-TripTM Circuit Breaker (Figure 7) The SMH4802 provides a Quick-Trip feature that will cause the circuit breaker to trip immediately if the voltage drop across RS exceeds VQCB. The Quick-Trip can be disabled or set to 60mV, 100mV (default) or 200mV. Current Regulation The current regulation mode is an optional feature that provides a means to regulate current through the MOSFET for a programmable period of time. It is generally enabled in applications that have switched dual (A and B) distributed power sources. By using the current regulation function unwarranted shutdowns can be avoided if one of the dual supplies is switched in when it is at a more negative potential than the currently operating supply. When current regulation is selected it will be enabled during soft start (power on period) and during normal operation after the PG# output is enabled. If the voltage monitored at the CBSENSE pin is greater than 50mV, but less than VQCB, the SMH4802 will reduce the VGATE voltage in order to maintain a CBSENSE potential less than 60mV, effectively regulating the current through the MOSFET. Figures 8A and 8B illustrate the current regulation function. The time period tPCR -- selectable at 5, 80, or 320ms -- is the maximum time during which regulation will be enforced. If either VQCB or tPCR are exceeded the VGATE and PG# outputs will immediately be de-asserted. However, if CBSENSE drops below 50mV before the timer ends, the timer is reset and VGATE resumes normal operation. If the Quick-Trip level is exceeded then the device will bypass the current regulation timer and shut down immediately. The Current Regulation feature is disabled in the default configuration. Operating at High Voltages The breakdown voltage of the external active and passive components limits the maximum operating voltage of the SMH4802 hot-swap controller. Components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the DRAIN SENSE pin, the power MOSFET switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller's VDD pin. Over-Voltage and Under-Voltage Resistors In Figure 9 the three resistors (R1, R2, and R3) connected to the OV and UV inputs must be capable of withstanding the maximum supply voltage of several hundred volts.
10
0V
2062 Fig08B
VQCB 50mV
CBSENSE
TQTSD VGATE
2062 Fig07
Figure 7. Circuit Breaker Quick Trip Response
VQCB CBSENSE
tPCR
50mV 0V tCRD 12V VGATE
0V
2062 Fig08A
Figure 8A. Current Regulation With Recovery
VQCB CBSENSE
tPCR
50mV 0V 12V VGATE
Figure 8B. Current Regulation Without Recovery
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
SMH4802
Preliminary Information
APPLICATIONS INFORMATION (Continued)
ISO2
FS
R9 Optional 100 Forced
SMX3200 Connector Header
2 1 4 3 5 J1 6 8 7 10 9
Shutdown Components
R5 47k
-48V Ret
RD R4 10k C5 0.01F
-48V Ret
5VREF 14
VDD
4
SDA
5
SCL
10
FS#
11
5VREF
R3 270k
R10 100k
8 UV
R2 10k
EN/TS
3 12
Q2 L14N1/TO
EN/TS ENABLE#
9
R1 10k
SMH4802
CBSENSE
PG#
OV
VGATE
VSS
7
6
C1 1F R7 10
2
DRAIN SENSE
1
R8 10k C3 47nF
R11 100k C2 0.1F D1
Optional DRAIN SENSE Components
R6 0.02
-48V
-48V Switched
2062 Fig09
Figure 9. Example Applications Schematic.
Pin numbers reflect SOIC package.
Notes: 1. The 10 resistor (R7) must be located as close as possible to the MOSFET. 2. Optional interface circuit (Q2). The PG# output can be directly connected to the power module if the input voltage to the module is within tolerance and the voltage on the PG# output doesn't exceed 15V. 3. If the DRAIN SENSE signal is not used tie the pin directly to V (pin 7).
SS
The trip voltage of the UV and OV inputs is 2.5V relative to VSS. Large value resistors can be used in the resistive divider as the input impedance of UV and OV is very high. The divider resistors should be high stability 1% metalfilm resistors to keep the under-voltage and over-voltage trip points accurate. Telecom Design Example A hot-swap telecom application may use a 48V power supply with a -25% to +50% tolerance (i.e., the 48V
supply can vary from 36V to 72V). The formulas for calculating R1, R2, and R3 are as follows. First, a peak current, IDMAX, must be specified for the resistive network. The value of the current is arbitrary, but it cannot be too high (self-heating in R3 becomes a problem) or too low (the value of R3 becomes very large, and leakage currents can reduce the accuracy of the OV and UV trip points). The value of IDMAX should be 200A for the best accuracy at the OV and UV trip points. A value
SUMMIT MICROELECTRONICS, Inc.
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SMH4802
Preliminary Information
APPLICATIONS INFORMATION (Continued)
of 250A for IDMAX is used to illustrate the following calculations. With VOV (2.5V) being the over-voltage trip point, R1 is calculated by the formula:
R1 = VOV IDMAX
Dropper Resistor Selection The SMH4802 is powered from the high-voltage supply via dropper resistor RD. The dropper resistor must provide the SMH4802 (and its loads) with sufficient operating current under minimum supply voltage conditions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. The dropper resistor value is calculated from:
RD = VSMIN - VDDMAX IDD - ILOAD
Substituting:
R1 = 2.5V = 10k 250 A
Next the minimum current that flows through the resistive divider, IDMIN, is calculated from the ratio of minimum and maximum supply voltage levels:
IDMIN = IDMAX x VSMIN VSMAX
where VSMIN is the lowest operating supply voltage, VDDMAX is the upper limit of the SMH4802 supply voltage, IDD is minimum current required for the SMH4802 to operate, and ILOAD is any additional load current from the 2.5V and 5V outputs and between VDD and VSS. Calculate the minimum wattage required for RD from:
PRO
Substituting:
250 A x 36V IDMIN = = 125 A 2.5V Now the value of R3 is calculated from IDMIN: R3 = VSMIN x VUV IDMIN
(VSMAX - VDD )
MIN
2
RD
where VDDMIN is the lower limit of the SMH4802 supply voltage, and VSMAX is the highest operating supply voltage. In circumstances where the input voltage may swing over a wide range (e.g., from 20V to 100V) the maximum current may be exceeded. In these circumstances it may be necessary to add an 11V Zener diode between VDD and VSS to handle the wide current range. The Zener voltage should be below the nominal regulation voltage of the SMH4802 so that it becomes the primary regulator. MOSFET VDS(ON) Threshold The drain sense input on the SMH4802 monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. When the MOSFET's VDS is below the user-defined threshold the MOSFET switch is considered to be ON. The VDS(ON)THRESHOLD is adjusted using the resistor RT in series with the drain sense protection diode. This protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the MOSFET switch is OFF. A low leakage MMBD1401 diode offers protection up to 100V. For high voltage applications (up to 500V) the Central Semiconductor CMR1F-10M diode should be used. The VDS(ON)THRESHOLD is calculated from:
VDS (ON)THRESHOLD = VSENSE - (ISENSE - RT ) - VDIODE
VUV is the under-voltage trip point, also 2.5V. Substituting:
36V x 2.5V = 286k 125 A The closest standard 1% resistor value is 267k R3 =
Then R2 is calculated:
2.5V R2 = - 10k = 20k - 10k = 10k 125 A or R2 = VUV - R1 IDMIN
Substituting:
2.5V - 10k = 20k - 10k = 10k 125 A An Excel spread sheet is available on Summit's website (www.summitmicro.com) to simplify the resistor value calculations and tolerance analysis for R1, R2, and R3. R2 =
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SMH4802
Preliminary Information
APPLICATIONS INFORMATION (Continued)
where VDIODE is the forward voltage drop of the protection diode. The VDS(ON)THRESHOLD varies over temperature due to the temperature dependence of VDIODE and ISENSE. The calculation below gives the VDS(ON)THRESHOLD under the worst case condition of 85C ambient. Using a 68k resistor for RT gives:
VDS (ON)THRESHOLD = 2.5V - (15 A x 68k ) - 0.5V = 1V
supply turns on, the RESET# output of the SMS44 would be released and FS# pulled high. However, if for any reason not all of the supplies turn on, RESET# is not released and the SMH4802 disables the PG# output. Soft Start Slew Rate Control The -48V turn on time is controlled by the SMH4802 and by the values of R8, C1 and C3 in Figure 9. The turn on time is approximately 10ms with the component values shown. Increasing the capacitance reduces the output slew rate and increases the turn on time. The capacitors prevent the MOSFET from turning on simultaneously with the application of -48V. Resistor R8 is specified to limit the current into and the rate of charge of C1. The ratio of C1 to C3 (20:1) limits the MOSFET's VGS to approximately 2V once the -48V supply is connected and C1 is fully charged.
The voltage drop across the MOSFET switch and sense resistor, VDSS, is calculated from:
VDSS = ID (RS x RON )
where ID is the MOSFET drain current, RS is the circuit breaker sense resistor and RON is the MOSFET on resistance. The dropper resistor value should be chosen such that the minimum and maximum IDD and VDD specifications of the SMH4802 are maintained across the host supply's valid operating voltage range. First, subtract the minimum VDD of the SMH4802 from the low end of the voltage, and divide by the minimum IDD value. Using this value of resistance as RD find the operating current that would result from running at the high end of the supply voltage to verify that the resulting current is less than the maximum IDD current allowed. If some range of supply voltage is chosen that would cause the maximum IDD specification to be violated, then an external zener diode with a breakdown voltage of 11V should be used across VDD. As an example of choosing the proper RD value, assume the host supply voltage ranges from 36 to 72V. The largest dropper resistor that can be used is: (36V-11V)/3mA = 8.3k. Next, confirm that this value of RD also works at the high end: (72V-13V)/8.3k = 7.08mA, which is less than 8mA. The FS# input can also be used in conjunction with a secondary-side supervisory circuit providing a positive feedback loop during the power up sequence. As an example, assume the SMH4802 is configured to turn on -48V to three DC/DC converters and then sequentially turn on the converters with a 1.6ms delay. Further, assume all of the enable inputs are true and PG# has just been sequenced on. If FS# option 4 (100BIN in register 5) has been selected, then FS# must be driven high within 1.6ms after PG# goes low, otherwise the PG# output is disabled. Ideally, there would be a secondary-side supervisor similar to the SMS44 that would have its reset time-out period programmed to be less than 1.6ms. After the last
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
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SMH4802
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
PROGRAMMING CONNECTION The SMH4802 uses the industry standard I2C 2-wire serial data interface. This interface provides access to the configuration registers and the nonvolatile fault latch. Device configuration utilizing the Windows based SMH4802 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMH4802. The Dongle connects directly to the parallel port of a PC and the target application. It programs the device through a cable using the I2C bus protocol. The SMX3200 system consists of a programming Dongle, cable and Windows GUI software. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website. When design prototyping is complete, the software can generate a HEX data file that should then be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMH4802 via the programming Dongle and cable. An example of the connection interface is shown in Figure 10. When design prototyping is complete the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application.
Caution: If the device is powered from -48V during programming damage may occur when connecting the dongle to a system utilizing an earth-connected positive terminal. Either disabling the -48V connection or using a laptop computer is the best way to avoid damage.
Top view of straight 0.1" x 0.1" closed side connector SMX3200 interface Pin 10, Reserved Pin 8, Reserved Pin 6, Reserved Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin5, Reserved Pin3, GND Pin 1, GND
-48V Ret. RD
VDD SMH4802 SDA VSS SCL -48V
10 8 6 4 2
9 7 5 3 1
C1 0.01F
2062 Fig10
Figure 10. SMX3200 Programmer I2C serial bus connections.
Pin numbers reflect SOIC package.
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SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
PROGRAMMING INFORMATION
I2C Bus Interface The I2C bus is a two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA) and a serial clock line (SCL). The SMH4802 supports a 100 kHz clock rate. The SDA line must be connected to a positive supply by a pull-up resistor located on the bus. The SMH4802 contains a Schmitt input on both the SDA and SCL signals. Start and Stop Conditions Both the SDA and SCL pins remain high when the bus is not busy. Data transfers between devices may be initiated with a Start condition only when SCL and SDA are high. A high-to-low transition of the SDA while the SCL pin is high is defined as a Start condition. A low-to-high transition on SDA while SCL is high is defined as a Stop condition. Figure 11 shows a timing diagram of the start and stop conditions.
START Condition SCL
SCL SDA 1 1 2 0 3 1 4 0 5 x 6 x 7 x 8 R/W 9 ACK
2062 Fig13
SCL
1
2
3
8
9
SDA Trans SDA Rec ACK
2062 Fig12
Figure 12. Acknowledge Timing Read and Write The first byte from a Master is always made up of a 7-bit Slave address and the Read/Write (R/W) bit. The R/W bit tells the Slave whether the Master is reading data from the bus or writing data to the bus (1 = Read, 0 = Write). The first four of the seven address bits are called the Device Type Identifier (DTI). The DTI for the SMH4802 is 1010BIN. The next three bits are Address values for A2, A1, and A0 (if multiple devices are used). The SMH4802 issues an Acknowledge after recognizing a Start condition and its DTI. Figure 13 shows an example of a typical master address byte transmission.
STOP Condition
SDA In
2062 Fig11
Figure 13. Typical Master Address Byte Transmission During a read by the Master device the SMH4802 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no Stop condition is generated by the Master, the SMH4802 continues to transmit data. If an Acknowledge is not detected (NACK) the SMH4802 terminates any subsequent data transmission. The read transfer protocol on SDA is shown in Figure 14. During a Master write the SMH4802 receives eight bits of data, then generates an Acknowledge signal. The device continues to generate the ACK condition on SDA until a Stop condition is generated by the Master. The write transfer protocol on SDA is shown in Figure 15. Random Access Read Random address read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condition and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4802 to the desired address.
15
Figure 11. Start and Stop Conditions Master/Slave Protocol The master/slave protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. The device controlling data transmission is called the Master, and the controlled device is called the Slave. In all cases the SMH4802 is referred to as a Slave device since it never initiates any data transfers. Acknowledge Data is always transferred in bytes. Acknowledge (ACK) is used to indicate a successful data transfer. The transmitting device releases the bus after transmitting eight bits. During the ninth clock cycle the Receiver pulls the SDA line low to acknowledge that it received the eight bits of data. This is shown by the ACK in Figure 12. When the last byte has been transferred to the Master during a read of the SMH4802 the Master leaves SDA high for a Not Acknowledge (NACK) cycle. This causes the SMH4802 part to stop sending data, and the Master issues a Stop on the clock pulse following the NACK.
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
SMH4802
Preliminary Information
PROGRAMMING INFORMATION (Continued)
After the word address Acknowledge is received by the Master it immediately reissues a Start condition followed by another Slave address field with the R/W bit set to Read. The SMH4802 responds with an Acknowledge and then transmits the 8 data bits stored at the addressed location. At this point, the Master sets the SDA line to NACK and generates a Stop condition. The SMH4802 discontinues data transmission and reverts to its standby power mode. Sequential Reads Sequential reads can be initiated as either a current address read or a random access read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read). However, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4802. The SMH4802 continues to output data for each Acknowledge received. The Master sets the SDA line to NACK and generates a Stop condition. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter rolls over and the memory continues to output data.
Master SDA Slave
S T A R T
R / W 1010xxxRxxx xxxxx A C K
A C K xx xx
N A C K
S T O P
Master SDA Slave
S T A R T
R / W 1 0 1 0 x x xW A C K xxxxxxxx A C K xx xx A C K
S T O P
2062 Fig14
2062 Fig15
Figure 14. Read Protocol
Figure 15. Write Protocol
Master SDA Slave
S T A R T
DEVICE IDENTIFIER
Typical Write Operation
S T O P DDDDDDDD 76543210
AA A R 1 0 1 0 21 0 / W
BUS ADDRESS
AAAAAAAA 76543210 A C K A C K
A C K S T A R T AA A R 1 0 1 0 21 0 / W DDDDDDDD 76543210 A C K
Master SDA Slave
S T A R T
DEVICE IDENTIFIER
Typical Read Operation
N A C K
S T O P
AA A R 10 1 0 21 0 / W
BUS ADDRESS
AA A A A A A A 76 5 4 3 2 1 0 A C K A C K
2062 Fig16
Figure 16. Sequential Bus Cycles
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2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
PROGRAMMING INFORMATION (Continued)
Register Access The SMH4802 contains a 2-wire bus interface for register access as explained in the previous section. This bus is highly configurable while maintaining the industry standard protocol. The SMH4802 responds to one of two selectable Device Type Addresses: 1010BIN, generally assigned to NV-memories, or 1011BIN, which is the default address for the SMH4802. The Device Type Address is assigned by programming bit 3 of Register 8. Register accesses are also programmable using bits 2 and 1 of Register 8. Accesses can be denied (no reads or writes), read only, or read/write (default state). The SMH4802 has three address pins (A2, A1 and A0) associated with the 2-wire bus. The SMH4802 can be configured to respond only to the proper serial data string of the Device Type Address and specific bus addresses (Register 8, bit 0 set); or to the Device Type Address and any bus address (Register 8, bit 0 cleared). Master/Slave Protocol The master/slave protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. The SMH4802 is always a Slave device since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because a change on the data line while SCL is high is interpreted as either a Start or a Stop condition. Register Bit Maps The SMH4802 has eight user programmable, nonvolatile configuration registers. Although 8-bit data transfers are used for reading and writing the registers, only the 4 least significant bits of each register are utilized by the device. Therefore, in each of the following registers, bits 7 through 4 are left blank. Bits 3 through 0 are used as shown for each register.
DEFAULT CONFIGURATION REGISTER SETTINGS - SMH4802-169
Register R02 R03 R04 R05 R06 R07 R08 R09 R0C
Hex Contents 9 2 B C C 9 1 9 0
Description Over-current delay and Quick-T ip over-current reference level. r Power good sequencing delay. CB mode enable. PG# enable, over-/under-voltage filter delay, circuit breaker cycle time. Non-volatile fault latch enable, FS# function control. Under- and over-voltage filter enables, VGA E current regulation control. T Under-voltage hysteresis control. I2C control, including device type address, configuration register read/write status, and slave address response control. Power good sequence speed. Non-volatile fault latch. Set by hardware when fault is detected.
2062 Reg Table
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
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SMH4802
Preliminary Information
PACKAGES
14 PIN SOIC PACKAGE
0.337 - 0.344 (8.55 - 8.75)
Ref. JEDEC MS-012 0.228 - 0.244 (5.80 - 6.20) Inches (Millimeters)
1
0.150 - 0.157 (3.80 - 4.00) X45 (0.25 - 0.50) 0 Min to 8 Max 0.016 - 0.050 (0.40 - 1.27) 0.05 (1.27) 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.01 (0.10 - 0.25)
14 Pin SOIC
0.053 - 0.069 (1.35 - 1.75)
0.01 - 0.02
0.0075 - 0.01 (0.19 - 0.25)
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SUMMIT MICROELECTRONICS, Inc.
SMH4802
Preliminary Information
PACKAGES (Continued)
16 PIN SSOP PACKAGE
0.189 - 0.197 (4.80 - 5.00)
Ref. JEDEC MO-137 0.228 - 0.244 (5.79 - 6.20) Inches (Millimeters) Pin 1
0.150 - 0.157 (3.81 - 3.99) 0.053 - 0.069 (1.35 - 1.75) 0.007 - 0.010 (0.18 - 0.25) 0 Min to 8 Max 0.016 - 0.050 (0.41 - 1.27) 0.025 (0.635) 0.008 - 0.012 (0.20 - 0.31) 0.059 MAX (1.50)
0.004 - 0.010 (0.10 - 0.25)
16 Pin SSOP
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
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SMH4802
Preliminary Information
ORDERING INFORMATION
SMH4802 S u m m it P a rt N u m b e r
S
nnn P a rt N u m b e r S u ffix (s e e p a g e 1 7 )
Package S=14 Lead SO IC G =16 Lead SSO P
S pecific requirem ents are contained in the suffix such as Com m ercial or Industrial T em p Range, Hex code, Hex code rev ision, etc.
PART MARKING
Summit Part Number
SUMMIT
.
SMH4802S xx
A nnn
Status Tracking (Blank, MS, ES, 01, 02, ...) (Summit Use) Date Code (YY WW) Lot Tracking Code (Summit Use) Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit Use)
A YY WW
NOTICE This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2003 SUMMIT Microelectronics, Inc. Power Management for CommunicationsTM Revision 2.3 - This Document supersedes all previous versions.
I2C is a trademark of Philips Corporation.
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2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc.

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